In integrated components which have clock generators and clock distribution networks for high frequencies, it is becoming more and more important to measure the quality of the clock generators and clock distribution networks. The quality of the clock generators and clock distribution networks is an important measured variable for fluctuations in production technology. Since these fluctuations may reduce the production yield of the integrated components, they must be measured, and thus detected, early. Due to the early detection, the production technology can be adapted so that the production yield is already increased in the early stages of running up production.
For high volume products having a short life cycle, particularly for short-lived consumer products, the detection of all relevant statistical data at a very early stage is very important. These data also include the period jitter parameter which is needed for the precise characterization of clock generators. Such a clock generator is constructed, e.g. as PLL (phase-locked loop) or as CDR (clock data recovery).
In the case of components in CMOS technologies having minimal pattern widths above 90 nm, the period jitter was frequently measured with high-resolution external test instruments during the characterization at individual test chips. In production, in contrast, this measurement was only taken at a selection of components, at the most.
For some applications, however, the measurement must be performed for all components during the production test. This applies, for example, to components which are installed in motor cars and in which the quality requirements are very high. Moreover, the external test instruments are very expensive; a production test using such external test instruments which would be performed for many components would unacceptably increase the test costs.
In US 2004/0061488, the jitter parameters of a PLL are generated with the aid of a module located on the integrated component. This module contains a ring oscillator of delay elements, a counter, which counts the number of clock cycles, being connected to the output of a signal delay element. A decoder which measures the subunits of the clock cycles is connected to the outputs of all delay elements. In this arrangement, however, the special requirements for highly precise measurements are not considered in which a resolution of the measurement of less than 10 picoseconds is required.
For these and other reasons, there is a need for the present invention.